About Me

Hi, I’m Jaewon, a 6th-year Ph.D. candidate in Computer Science at Georgia Tech, advised by Professor Hyesoon Kim. My research focuses on computer architecture, specifically optimizing memory safety mechanisms for GPUs through hardware/software co-design. I also have over five years of experience as an SoC Performance Architect in Samsung S.LSI, where I specialized in SoC performance simulation and optimization.

EDUCATION

Georgia Institute of Technology, Aug 2019 – Present.

• Doctor of Philosophy (PhD), Computer Science
• Advisor: Hyesoon Kim
• Specilized in Computer Architecture.

Georgia Institute of Technology, Aug 2022 – Jul 2024.

• Master of Science (MS), Computer Science
• Specilized in Machine Learning.

RESEARCH

Computer Architecture with a focus on GPU and security

• Proposed the first hardware-software co-designed GPU memory safety mechanism.
• Leveraged LLVM static-time analysis for kernel buffer identification and metadata access minimization.
• Designed runtime library support for secure, dynamic bounds table management.
• Hardware runtime bounds checking using a two-level bounds cache and min-max address coalescing.

Work Experience

SoC Performance Architect, Samsung S.LSI – S.Korea, Sep 2014 – Aug 2019

• Led pre-silicon performance simulation and optimization for SoC architecture, with a focus on system parameter tuning to achieve optimal performance.
• Designed traffic generators to model memory access patterns for multimedia IPs, improving simulation accuracy.
• Optimized Network-on-Chip (NoC) reorder buffer size by analyzing real-time memory access patterns of manager IPs, reducing NoC area by 11%.
• Enhanced an in-house cycle-accurate simulator by implementing Transaction-level Modeling (TLM) synchronization, significantly speeding up simulation performance.
• Conducted post-silicon power and performance characterization on ARM-based Linux/Android platforms using benchmarks such as SPEC2017 and CoreMark, along with tools like ADB and NI DAQ.

Highlighted Research Publication

• Jaewon Lee, Yonghae Kim, Jaishen Cao, Euna Kim, Jaekyu Lee, Hyesoon Kim. 2022. Securing GPU via region-based bounds checking. (ISCA ‘22). In Proceedings of the 49th Annual International Symposium on Computer Architecture. Association for Computing Machinery, New York, NY, USA, 27–41. Nominated for the Best Paper Award.
• Ruobing Han, Jaewon Lee, Jaewoong Sim, Hyesoon Kim. 2022. COX: Exposing CUDA Warp-Level Functions to CPUs (TACO ‘22). ACM Transactions on Architecture and Code Optimization.
• Jaewon Lee, Hanning Chen, Jeffrey Young, Hyesoon Kim RISC-V FPGA Platform Toward ROS-Based Robotics Applications (FPL ‘20 Workshop). 2020 30th International Conference on Field-Programmable Logic and Applications.

Opensource Projects

Vortex: OpenCL-Compatible RISC-V GPGPU

• Designed a 32b/64b virtual memory system for Vortex SimX, a C++ cycle-level simulator.
• Implemented virtual-to-physical page mapping and a page table walk mechanism.

Macsim: Heterogeneous CPU/GPU Architecture Simulator

• Modeled virtual-to-physical address translations in the GPU, including TLB support.
• Enabled Macsim to parse NVIDIA GPU traces generated by NVBit.